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A Java chip available -- now!

  • April 8, 1999
  • By Rick Brian Slack
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Java software development is in high gear as acceptance of this robust "write once, run anywhere" language continues to accelerate. But where's the hardware that will allow Java to run at the speeds users rightfully expect and will eventually demand? And what about hardware to support all these new-wave "Internet appliances" where Java is planned to serve as the backbone?

The reality is that it's already here! Patriot Scientific Corp. offers the PSC1000; a microprocessor originally designed to run C and FORTH (which it does efficiently) that just happens to execute Java at native speeds.

The Patriot PSC1000A Java microprocessor is the only true low-cost, high-performance, native Java processor currently available. It is ideal for Internet-enabled information kiosks, cell and video phones, embedded Web servers, set-top boxes, and a host of other new Internet appliances. The 32-bit microprocessor, based on Patriot's patented ShBoom technology, is designed to provide cost-efficient solutions for the growing number of new Java applications, as well as other traditional embedded systems markets.

"We are pleased to see [Patriot] incorporating JavaOS into their cutting-edge PSC1000 microprocessor," said David Spenhoff, director of product marketing and field communications for Sun Microsystems' JavaSoft division. "Patriot's microprocessors make the development of exciting, Internet-enabled, Java-based products possible."


The PSC1000 Microprocessor is a highly integrated 32-bit RISC processor that offers the ability to run Java programs at native performance levels.


The PSC1000 is currently available in a .5-micron configuration, runs at 100 MHz, and is available in 5-volt and 3.3-volt versions. The next-generation .35-micron configuration of the microprocessor is expected to be available soon, running in the 150-MHz range. All the "nitty-gritty" detailed information provided below pertains to the current .5-micron PSC1000.

The nitty-gritty

The PSC1000 Microprocessor is a highly integrated 32-bit RISC processor that offers the ability to run Java programs at native performance levels, as well as retaining excellent performance for C and FORTH applications. It provides unparalleled price/performance for a wide range of embedded applications. This unique architecture is a blend of the best of stack and register-based designs, enabling features such as 8-bit instructions for enhanced performance and optimal code size. The 32-bit registers and data paths fully support 32-bit addresses and data types. It addresses up to four gigabytes of physical memory, and supports virtual memory with the use of external mapping logic.

The PSC1000 is targeted for embedded applications that require high Microprocessing Unit (MPU) performance and low system cost. In particular, the PSC1000 is ideal for Java-based devices and other nontraditional applications of Internet connectivity. Until now, Internet connectivity has required expensive servers to provide information and desktop computers to access that information. The PSC1000's outstanding price and native Java performance will enable low-cost devices to connect to the Internet. Examples of clients or browsers that will gain access to information on the Internet include personal digital assistants, set-top cable boxes and "smart" cell phones. On the server side, many common devices will be connected to the Internet for monitor and control purposes. This will be accomplished via tiny embedded Web servers, which will allow information from these devices to be viewed on the Internet via any standard browser. Examples of devices that will greatly benefit from monitor and control via standard Internet protocols include laser printers, network routers, factory floor machinery, security systems, even household appliances such as refrigerators. In addition, the PSC1000 is well suited to a variety of traditional embedded systems such as graphics accelerators, motor controls, factory floor controllers, automotive applications, and many others.

The PSC1000 MPU contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top element, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement typical of register-based architectures and also minimize memory accesses during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.

The PSC1000 Central Processing Unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle, without the use of pipelines or superscalar architecture. A "flow-through" design allows the next instruction to start before the prior instruction completes, thus increasing performance. The PSC1000 CPU operates up to four groups of programmable bus configurations from as fast as 20 ns to as slow as 820 ns, allowing any desired mix of high-speed and low-speed memory. Minimum system cost is reduced, thus allowing the system designer to trade system cost for performance as needed.


By incorporating many on-chip system functions and a "glueless" bus interface, support chips are eliminated, further lowering system cost.


The PSC1000 CPU architectural philosophy is that of simplification and efficiency of use. A zero-operand design eliminates most operand bits, and the decoding time and instruction space they require. Instructions are shrunk to 8-bits, significantly increasing instruction bandwidth and reducing program size. By not using pipeline or superscalar execution, the resulting control simplicity increases execution speed to issue and complete an instruction in a single clock cycle, as often as every clock cycle, without a conventional instruction cache. To ensure a low-cost chip, a data cache and its cost are also eliminated in favor of efficient register caches.

By incorporating many on-chip system functions and a "glueless" bus interface, support chips are eliminated, further lowering system cost. The CPU includes an MPU, an I/O processor, a DMA controller, an interrupt controller, bit inputs, bit outputs, and a programmable memory interface. It can operate with 32-bit-wide and 8-bit-wide memory and devices, and includes hardware debugging support. A minimum system consists of a PSC1000 CPU, an 8-bit-wide EPROM, an oscillator, and optionally one x8 or two x16 memories -- a total of four or five active components. The small die, which contains only 137,500 transistors, produces a high-performance, low-cost CPU, and a high level of integration produces a high-performance, low-cost system.

More information and a downloadable data sheet on the PSC1000 are available from the Patriot Scientific Web site. Full reference documentation is available in evaluation kits, which include an evaluation board, as well as all development tools for the PSC1000.







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